Transient electro-thermal simulation of a three dimensional integrated circuit (3DIC) isreported that uses a cell-based simulation to provide a selected transistor thermal profile whileproviding advantages of hierarchical simulation. Due to CPU and memory limitations, fulltransistor electro-thermal simulations on a useful scale are not possible. Standard cells areconsidered on a per-instance basis and modeled with electro-thermal macro-models developedin a multi-physics simulator. Simulations are compared favorably to measurements for a token-generating 3DIC clocking at a maximum of 1 GHz. The 3DIC, which is composed of 9 by 3layers of repetitive frequency multipliers and dividers, was fabricated with the MassachusettsInstitute of Technology Lincoln Laboratory (MITLL) 3DIC process.